1. Field of the Invention
The present invention relates to a gating circuit and in particular to a clocked digital pulse gating mechanism for use within serial data re-synchronization circuitry.
2. Description of the Related Art
Referring to FIG. 1A, it is well known in the art to recover a periodic clock waveform from a pseudo-random, asynchronous data source with a phase-locked loop (PLL) 100 in serial data clock recovery and data re-synchronization applications. PLL 100 typically includes a phase comparator 108, a low pass filter (LPF) 109, and a voltage controlled oscillator (VCO) 110. Phase comparator 108 compares two input frequencies provided initially on lines 105 and 103 and passed through delay line 107 and clock gate 111, respectively. Phase comparator 108 then generates an output phase-error signal that is determined by the phase difference between these two frequencies. If the frequency on line 105 does not equal the frequency on line 103, the phase-error signal, after being filtered by LPF 109, causes the frequency of VCO 110 to deviate in the direction of the frequency on line 105. If PLL 100 is properly designed, VCO 110 locks to the frequency on line 105 and ignores the missing pulses (zeroes) of the pseudo-random data. The recovered clock waveform 103.sub.w (FIG. 1B) generated by PLL 100 frames each delayed pulse with its falling edges. This provides a "window" 120 for every bit (see waveforms 105.sub.w and 112.sub.w which represent signals provided on lines 105 and 112, respectively). Note that an input data pulse typically represents a logic one while the absence of a pulse typically represents a logic zero. LPF 109 largely ignores the jitter of individual bits within these clocked windows, thereby maintaining the center of window 120 about the average bit position and ensuring proper detection of most bits.
The bit capture circuit (hereinafter referred to as data latch 101), is provided raw, unsynchronized data on line 112 (via delay line 107 from line 105) and a recovered clock signal on line 103. Data latch 101 captures the data bits on line 112 and then transmits these bits as re-synchronized data on line 102 (see waveform 102.sub.w).
Data latch 101 has the following requirements:
1. a very small metastability region at the window boundaries for minimum decision loss, PA1 2. a rapid recovery from transmission of each bit for maximum transfer rate capability (high pulse repetition rate), and PA1 3. an NRZ (non-return-to-zero) output pulse. PA1 1. the propagation delay of a logic one signal on line 406 from the clock input terminal CK on flip-flop 401 to a logic one at its Q-output terminal, plus the set-up time of a logic one at the D-input terminal of flip-flop 402, or PA1 2. the propagation delay of a logic zero signal on line 406 from the clock input terminal CK on flip-flop 401 to a logic zero at its Q-output terminal, plus the set-up time of a logic zero at the D-input terminal of flip-flop 402.
Ideally, even if two bits in adjacent windows, for example bits 126 and 127 in windows 120C and 120D, respectively, are pushed toward each other, almost to the point where the two bits meet at the common boundary 125, bits 126 and 127 should still be properly recognized by data latch 101. In other words, the data latch recovery (reset) time from transmittal of any single bit until it is ready for the next data bit should approach zero, therefore allowing for maximum data throughput and jitter tolerance.
FIG. 2A illustrate a data latch 200 known in the art which includes flip-flops 201 and 202. Assuming a logic one signal is provided to input data terminal D via line 203, the signal on the Q-output terminal of flip-flop 201 is set to a logic one if a data bit is provided on line 204. By definition, this logic one is also subsequently provided on the data input terminal D of flip-flop 202. The next clock edge on line 206 (waveform 206.sub.w of FIG. 2B) transfers this logic one signal to the Q-output terminal of flip-flop 202 and clears flip-flop 201 via line 208. However, although data latch 200 provides the appropriate output pulse width 210 for waveform 205.sub.w, data latch 200 fails to identify data pulses, for example the second bit in each pair 212/213 and 214/215, which occur at or faster than the clock frequency (waveform 206.sub.w). Therefore, bits must be spaced apart by at least one empty window 220 to allow the signal on the Q-output terminal of flip-flop 202 to fall low and release the clear on flip-flop 201. Thus, bits 211, 212, and 214 are detected by data latch 200 while bits 213 and 215 remain undetected. Although this is acceptable for some types of channel encoding schemes, data latch 200 excludes those schemes which incorporate data at the clock frequency. Moreover, even if the bits are spaced apart by at least one empty window 220, such as bits 211 and 212 on waveform 204.sub.w, data latch 200 may yield errors because of jittery data in which random noise pushes bits into positions closer together than data latch 200 can tolerate.
Referring to FIGS. 3A and 3B, another known data latch 300 includes three flip flops 301, 302 and 303 in a backlash clear scheme as explained in detail below. Flip-flop 301 is used as a bit trap, i.e. the signal of the Q-output terminal of flip-flop 301 is set to a logic one when a data bit, for example bit 311, is provided on line 305. The next clock edge provided on line 306 to the clock input terminals CK of flip-flops 302 and 303 at time 330 (FIG. 3B) sets the signal of the Q-output terminal of flip-flop 302 to a logic one which in turn clears all flip-flops via line 308. Clearing flip-flop 303 triggers the synchronized data output pulse SD2 (waveform 307.sub.w) at the Q-output of flip-flop 303. Because the "clear" pulse is typically very short, flip-flop 301 is ready to receive data a full clock period sooner than data latch 201 of FIG. 2. At time 331 (FIG. 3B), the rising clock edge sets the signal of the Q-output terminal of flip-flop 303 to a logic zero, thereby ending the synchronized data pulse 316.
Flip-flop 301 cannot accept new data until approximately two gate delays (i.e. the propagation delay of a signal from the data input terminal D to the Q-output terminal of flip-flop 302 and the clear-release time of flip-flop 301) following the rising clock edge at time 330 (waveform 306.sub.w). Thus, from the time bit 311 in window 320A first clocks flip-flop 301 until the time flip-flop 301 is cleared and released, a "blind spot" encroaches into window 320B. As transfer frequency is increased and window size shrinks, this blind spot can encroach over an appreciable percentage of the next window. Thus, as shown in FIG. 3B, although bits 311, 312, 313 and 314 are detected (see pulses 316, 317, 318 and 319, respectively, on synchronized data waveform 307.sub.w), bit 315 remains undetected. Thus, window truncation inhibits high frequency data transmission and increases the error rate in jittery data.
FIG. 4 illustrates another prior art data latch 400 which includes flip-flops 401, 402, 403 and an XOR gate 404. In data latch 400, flip-flop 401 is not tripped and cleared with each input data bit, but instead is only toggled with the rising edges of the input data bits. In the absence of any input data, the signals on all the Q-output terminals of flip-flops 401, 402 and 403 are in the same logic state. For simplicity, assume all flip-flops have logic zero signals on their Q-output terminals. An incoming data bit 411 on line 406 (see waveform 406.sub.w in FIG. 4B) toggles the signal of the Q-output terminal of flip-flop 401 to a logic one. The rising clock edge (waveform 407.sub.w) at time 421 sets the signal on the Q-output terminal of flip-flop 402 to a logic one. Thus, flip-flop 402 and flip-flop 403 now have signals of opposite logic states on their Q-output terminals. These signals are in turn provided to the two input terminals of XOR gate 404. With these input signals, XOR gate 404 transmits a logic one signal on output line 405, thereby initiating the synchronized data output pulse 416 (waveform 405.sub.w in FIG. 4B). The next clock edge at time 422 clocks the signal on the Q-output terminal of flip-flop 403 to a logic one. Because both input signals to XOR gate 404 are logic ones, XOR gate 404 provides a logic zero output signal on line 405, thereby terminating synchronized data pulse 416. Note that pulse 416 is exactly the width of one clock window 420 because both the rising and falling edges of pulses 416 experience the same number of gate delays relative to the incoming clock signal (see waveform 407.sub.w).
Bits arriving at the clock frequency, for example bits 412 and 413 of waveform 406.sub.w, produce a continuous logic one signal (pulse 417) on output line 405 (waveform 405.sub.w). This logic one output signal is a desired response to adjacent pulses in the input data pattern. Note that in this configuration, bits (such as bits 414 and 415) may be spaced significantly closer than the clock period, i.e. window 420. Because there is no encroachment of window 420F, for example, into window 420G, even if bit 414 arrives just before a clock edge 430 and bit 415 arrives just after the clock edge 430, both bits are detected and result in a contiguous pulse 418 on waveform 405.sub.w. Additional information regarding the operation of data latch 400 is disclosed in U.S. Pat. No. 5,172,397, issued Dec. 15, 1992, and is herein incorporated by reference in its entirety.
Because flip-flops 401, 402 and 403 are not cleared, the blind spot created by the data latch 300, for example, is eliminated. Moreover, flip-flops 401, 402 and 403 operate at half the frequency of their counterparts in FIGS. 2A and 3A.
However, data latch 400 is preferably implemented in differential emitter-coupled logic (ECL) because propagation delays in this form of logic are independent of the direction of edge transition (e.g., the propagation delay from a flip-flop clock input to a positive transition at its Q output is equal to the propagation delay between the clock input and the negative transition at the Q output). This is significant because data window boundaries are alternately defined by the following periods:
In differential ECL logic, periods 1 and 2 are substantial equal. ECL has the disadvantages of being physically larger and consuming significantly more power than CMOS logic. However, if data latch 400 is implemented in single-ended CMOS technology, achieving substantially equal time delays for periods 1 and 2 is difficult, and frequently results in a skew in size between odd-bit windows and even-bit windows.